1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a mask ROM and fabrication method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for forming a bit line of a conductive material such as polysilicon to minimize device size and to enhance resistance characteristics.
2. Discussion of the Related Art
Typically, a flat ROM device is named after its structure. The name of the device is attributed to a fact that a step difference of a shape of bit and word lines is smaller than that of another memory device. A mask ROM is the name for specific coding selectively performed to set a specific cell to 0 or 1 through a mask process. Yet, it does not matter that the flat form is used together with the mask ROM.
A mask ROM and fabrication method thereof are explained with reference to the attached drawings as follows.
FIG. 1A is a cross-sectional diagram of a bit line of a mask ROM according to a related art, and FIG. 1B is a cross-sectional diagram of a word line of a mask ROM according to a related art.
Referring to FIG. 1A, in observing a mask ROM according to a related art in a bit line direction, a plurality of word lines are patterned over a substrate 10 having a gate oxide layer 12 formed thereon to leave a prescribed width from one another. Each of the word lines consists of a stack of polysilicon 13a and silicide 14a. 
Referring to FIG. 1B, in observing a mask ROM according to a related art in a word line direction, a gate oxide layer 12 is formed on a substrate 10 having a BN (buried N-doped) junction region 11 defined on a prescribed area. A polysilicon layer 13 and silicide 14 are sequentially stacked on the gate oxide layer 12. The gate oxide layer 12 over the BN junction region 11 is formed relatively thicker than the other portion. The BN junction region 11 buried in the substrate 10 plays the role of a bit line.
The above-explained mask ROM of the related art is fabricated in a following manner.
First, a device isolation area (not shown in the drawing) is formed on a semiconductor substrate 10 by LOCOS (local oxidation of silicon) or STI (shallow trench isolation). An area of the semiconductor substrate 10 excluding the device isolation area is defined as an active area.
Subsequently, a well is formed in the active area. A nitride layer (not shown in the drawing) is deposited on the semiconductor substrate 10. A photoresist pattern is formed on the nitride layer. The nitride layer is patterned to correspond to a width of the photoresist pattern. Ion implantation is then carried out on a prescribed portion of the semiconductor substrate 10 to define an impurity region using the patterned nitride layer as a mask. The defined impurity region corresponds to a BN (buried N doped) junction region 11.
After the patterned nitride layer has been removed, the semiconductor substrate 10 is cleaned. A gate oxide layer 12 is formed on the semiconductor substrate 10. In doing so, a portion of the gate oxide layer 12 formed on the BN junction region 11 is formed thicker than the other portion of the gate oxide layer 12.
A polysilicon layer 13 is formed on the gate oxide layer 12. A silicide 14 is formed by performing silicidation on the polysilicon layer 13. The silicide 14 and the polysilicon layer 13 are then selectively removed to form a silicide layer 14a and a gate electrode layer 13a, respectively. The silicide layer 14a is formed on the gate electrode layer 13a to form a stack. The stack consisting of the silicide stack 14a and the gate electrode layer 13a functions as a word line.
Subsequently, a gap between a pair of the stacks is filed up with an insulating layer 15.
Ion implantation is performed to form an LDD region and a heavily doped junction region.
In fabricating the flat cell type mask ROM according to the related art, the BN junction region 11 used as a bit line is formed by implanting ions into a pure active area and by annealing the ion-implanted region.
A region between a pair of the BN junction regions 11 functioning as bit lines, respectively corresponds to a channel of a cell transistor. A pair of the BN junction regions 11 are operative as source and drain, respectively.
The BN junction region 11 is formed relatively long in the flat cell type mask ROM. Inter-line resistance of the BN junction region 11 has considerable bad influence on driving a cell. To maintain the appropriate resistance, a junction depth and a line width need to be appropriately adjusted. Yet, as a cell size is reduced, it is difficult to appropriately implement the junction depth and line width in aspect of channel margin.